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KSIĘGARNIA NAUKOWO - AKADEMICKA

Digital structures for high-speed signal processing

58,00 

Seria: Monografie nr 141

ISBN/ISSN: 978-83-7348-505-1

Rok publikacji: 2013

Stron: 262

Opis

Digital structures for high-speed signal processing

Wydawnictwo Politechniki Gdańskiej

Czyżak Maciej

 

 

 

Słowa kluczowe: processing, high, signal, speed

 

CONTENTS

LIST OF IMPORTANT SYMBOLS AND ACRONYMS

  1. INTRODUCTION

1.1. Motivation and subject of the work

1.2. Contents of the dissertation

  1. REVIEW OF THE FIELD OF DIGITAL SIGNAL PROCESSING

2.1. Signal processing and digital signal processing

2.2. General structure of DSP systems

2.2.1. Exemplary structures of signal processing systems

2.2.2. Basic structure of DSP systems

2.3. A note on arithmetic operations in DSP

2.4. Summary

  1. CRITICAL REVIEW AND ANALYSIS OF SELECTED RESIDUE

NUMBER SYSTEMS  

3.1. A note on number systems

3.2. Residue number systems

3.3. Selected residue number systems

3.3.1. Polynomial mappings

3.3.2. Quadratic Residue Number System

3.3.3. Modified Quadratic Residue Number System

3.3.4. Quadratic-Like Residue Number System

3.3.5. Flexible Modulus Residue Number System

3.3.6. Polynomial Residue Number System

3.3.7. Moduli Replication Residue Number System

3.3.8. Algebraic Integer Residue Number System

3.4. Core function

3.5. Index calculus in GF(m)

3.6. Zech logarithms

3.7. Summary

  1. BINARY-TO-RESIDUE CONVERSION

4.1. Introduction

4.2. Binary-to-residue conversion

4.3. Preprocessing stage

4.3.1. Segmentation of input word

4.3.2. Evaluation of segmentation effects for five-bit moduli

4.3.3. Structures of Segment Modulo Generators

4.3.4. Simplification of preprocessing stage using common terms of neighbouring

segments

4.4. Pipelined Two-Operand Modulo Adders

4.4.1. Pipelined TOMA based on Ripple-Carry Adder

4.4.2. Pipelined TOMA based on Parallel-Prefix Adder

4.4.3. Pipelined TOMA based on Hiasat two-operand modulo adder

4.4.4. New five-bit TOMA

4.5. Multi-operand modulo adders

4.6. Final Modulo Generators

4.7. B/RNS converter based on Unified Channel Structure

4.8. B/RNS converter based on Per(m) approach

4.9. Comparison of approaches based on UCS and Per(m)

4.10. Two’s Complement System TCS/RNS converter

4.10.1. Conversion of signed binary numbers to RNS

4.10.2. Algorithm of TCS/RNS conversion

4.10.3. Architecture of TCS/RNS converter

4.11. Summary

  1. RESIDUE-TO-BINARY CONVERSION

5.1. Introduction and review

5.2. RNS/B converter based on CRT and CSA tree output reduction

5.3. RNS/B converter based on magnitude index calculation

5.4. RNS/B converter with quasi-regular structure based on CRT

5.5. RNS/B converter based on core function

5.5.1. Basic properties of core function and the principle of new B/RNS conversion

5.5.2. RNS/B conversion algorithm and converter architecture

5.6. Summary

  1. FAST MODULAR MULTIPLICATION FOR SMALL MODULI

6.1. Introduction

6.2. Basic blocks of five-bit Modular Multipliers (MMs)

6.3. Basic architectures of five-bit MMs

6.4. Architecture of new five-bit MM

6.5. Design of five-bit MMs by a constant

6.6. Comparison of five-bit MMs

6.7. Summary

  1. RESIDUE SCALING AND SMALL RANGE NON-ITERATIVE RESIDUE DIVISION

7.1. Introduction

7.2. Scaling basics

7.3. Fast parallel scaling based on magnitude index computation

7.3.1. Scaling algorithm

7.3.2. Scaling error evaluation and reduction

7.3.3. Scaler architecture

7.3.4. Scaler hardware amount and delay evaluation

7.4. Scaling of signed residue numbers based on MRS

7.5. Scaling of signed numbers based on the CRT

7.5.1. Error impact analysis of approximate CRT conversion

7.5.2. Scaling with the use of approximate projections

7.5.3. Scaler architecture

7.5.4. Analysis of scaler hardware amount and delay

7.6. Improved non-iterative residue division for small number ranges

7.6.1. Multiplicative residue division algorithm

7.6.2. Improved multiplicative residue division algorithm

7.7. Summary

  1. SELECTED RESIDUE NUMBER SYSTEM APPLICATIONS FOR FAST DIGITAL

SIGNAL PROCESSING  

8.1. TCS//RNS converter

8.2. RNS/B converter

8.3. Residue scaler

8.4. Residue divider

8.5. RNS FIR filter

8.6. FFT pipelined processor based on the modified quadratic residue number system

8.7. Example of spectral analysis of transformer inrush and short-circuit currents

with radix-4 MQRNS FFT processor

8.7.1. Introduction

8.7.2. Theoretical analysis of transformer inrush current

8.7.3. Theoretical analysis of transformer short-circuit current

8.7.4. On-line spectral analysis

8.8. Summary

  1. SUMMARY AND CONCLUSIONS

Summary in English

Summary in Polish

Appendix 1. Segmentation results for m = 17, 19, 23, 25, 27 and the chosen wordlength of input

words l = 12, 14, 16, 24, 32 and b = 1, 2, 3, 4

Appendix 2. Exemplary synthesis results for multipliers by a constant

Appendix 3. A note on origin and the initial period of digital signal processing

REFERENCES  

 

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